The present invention comprises an improvement over the cross-checking method and apparatus disclosed in the related parent application, namely U.S. patent application Ser. No. 07/650,791, entitled "On-The-Fly Error Correction with Embedded Digital Controller" now U.S. Pat. No. 5,241,546, the disclosure of which is incorporated herein by reference, (hereinafter referred to as "the referenced patent").
As disk drive areal densities increase, the goal of maintaining low data error rates becomes more difficult. At the same time, increased data throughput rates have led to on-the-fly error correction processes. The use of a 112 bit single and double burst Reed-Solomon on-the-fly error correction code techniques, as described in the referenced patent application, remains a presently preferred manner for detecting and correcting such error bursts.
In an on-the-fly error correction processing environment, once an error condition is detected within a data block, the error correction code remainder bytes, and the cross-check remainder bytes, for that block as obtained by the ECC and cross-check hardware, are latched, and are transferred to an ECC-tasked on-board microcontroller. The block having the detected data error condition is transferred to a temporary block storage location within an on-board block buffer memory array. The ECC and cross-check hardware receives and processes the next block of data incoming from the disk surface.
Simultaneously with the on-going data transfer, the ECC firmware executed by the microcontroller locates and corrects the error or errors and tests the correction with cross-check syndrome bytes which are updated in light of the corrections made to the data bytes. Once the correction process is tentatively completed, a cross-checking process is carried out. If the computational results of the cross-checking process are found to be equal to a reference value, such as zero, the cross-checking process ostensibly determines that the correction is valid, and that a miscorrection has not occurred. Since the cross-check syndrome bytes are based upon a different Reed Solomon generator polynomial than the one employed to generate the ECC syndrome bytes, it is hoped that only proper data corrections will be detected by the cross checking process. Unfortunately, the cross-checking process is susceptible to determination of a correction, whereas a miscorrection has in fact occurred.
The possibility of miscorrection is statistically derived and is known as the "miscorrection probability". A very low miscorrection probability is highly desirable, as miscorrection of erroneous data otherwise results in erroneous data being put out. While a cross-checking process is one known way to determine if a miscorrection has occurred in the ECC process, the cross-checking process may include weaknesses which increase the miscorrection probability.
In the prior approaches as disclosed, for example, in the Tenengolts U.S. Pat. No. 4,782,490, and in the referenced patent, the cross-checking algorithms provided two cross check bytes, each of which separately checked for miscorrection within a cross check interleave of each corrected data block. In that prior approach, there were three Reed-Solomon ECC interleaves within each data block and two cross check interleaves (odd data bytes, and even data bytes) within the same data block, with one cross check byte assigned to the odd bytes cross check interleave and the other cross check byte assigned to the even bytes cross check interleave.
With the prior eight-bit cross check byte approach, the misdetection probability of the cross-checking methodology was determined to be one out of 256 (or 3.9.times.10.sup.-3). In other words, if the cross-check bytes erroneously became convoluted in such a way that the syndrome becomes zero as a result of a miscorrection, a misdetection occurred; and, that possibility of misdetection existed with a probability of one out of 256.
While a misdetection probability of one out of 256 has been deemed to be adequate to confirm proper correction of most error burst patterns, some error burst patterns have been found which require a greater misdetection capability. For example, if a series of error bursts occurred within the same ECC interleave and also within the same cross check interleave (which can happen if the errors occur at multiples of six apart), the possibility of misdetection arises, and a miscorrection may occur which goes undetected by the cross check procedure. The prior cross-checking methodology has been determined to be ineffectual in detecting miscorrection of such error burst patterns. Thus, a hitherto unsolved need has remained for an error detection method and system which extends the probability of detecting miscorrections occurring within an error correction process, such as Reed-Solomon ECC, or other process such as another cyclic error correction code.